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IS41C16257 IS41LV16257
256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
FEATURES
* * * * * * Fast access and cycle time TTL compatible inputs and outputs Refresh Interval: 512 cycles/8 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden JEDEC standard pinout Single power supply: -- 5V 10% (IS41C16257) -- 3.3V 10% (IS41LV16257) Byte Write and Byte Read operation via two CAS Industrial temperature available
ISSI
MAY 1999
(R)
DESCRIPTION
The ISSI IS41C16257 and the IS41LV16257 are 262,144 x 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 512 random accesses within a single row with access cycle time as short as 12 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes these devices ideal for use in 16- and 32-bit wide data bus systems. These features make the IS41C16257 and the IS41LV16257 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C16257 and the IS41LV16257 are packaged in a 40-pin, 400-mil SOJ and TSOP (Type II).
* *
KEY TIMING PARAMETERS
Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. Fast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -35 35 10 18 12 60 -60 60 15 30 25 110 Unit ns ns ns ns ns
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
DR004-1B 05/24/99
1
IS41C16257 IS41LV16257
FUNCTIONAL BLOCK DIAGRAM
OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC OE
ISSI
CAS WE
(R)
RAS
RAS CLOCK GENERATOR
DATA I/O BUS
REFRESH COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS SENSE AMPLIFIERS
I/O0-I/O15
MEMORY ARRAY 262,144 x 16
ADDRESS BUFFERS A0-A8
PIN CONFIGURATIONS 40-Pin TSOP (Type II)
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8
PIN DESCRIPTIONS 40-Pin SOJ
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 GND
A0-A8 I/O0-I/O15
Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Power Ground No Connection
WE OE RAS
UCAS
LCAS
Vcc GND NC
NC NC WE RAS NC A0 A1 A2 A3 VCC
11 12 13 14 15 16 17 18 19 20
30 29 28 27 26 25 24 23 22 21
NC LCAS UCAS OE A8 A7 A6 A5 A4 GND
NC WE RAS NC A0 A1 A2 A3 VCC
2
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IS41C16257 IS41LV16257
TRUTH TABLE
Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) Read-Write(1,2) Hidden Refresh2)
ISSI
RAS
H L L L L L L L Read LHL Write LHL L HL
(R)
LCAS UCAS
H L L H L L H L L L H L H L H L L H L L L L H L
WE
X H H H L L L HL H L X X
OE
X L L L X X X LH L X X X
Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X
RAS-Only Refresh
CBR Refresh(3)
I/O High-Z DOUT Lower Byte, DOUT Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DOUT DIN Lower Byte, DIN Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DIN DOUT, DIN DOUT DOUT High-Z High-Z
Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. At least one of the two CAS signals must be active (LCAS or UCAS).
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IS41C16257 IS41LV16257
FUNCTIONAL DESCRIPTION
The IS41C16257 and the IS41LV16257 are CMOS DRAMs optimized for high-speed bandwidth, low-power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 18 address bits. These are entered nine bits (A0-A8) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used to latch the latter nine bits. The IS41C16257 and the IS41LV16257 has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generate a CAS signal functioning in an identical manner to the single CAS input on the other 256K x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 - I/O7 and UCAS controls I/O8 - I/O15. The IS41C16257 and the IS41LV16257 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C16257 both BYTE READ and BYTE WRITE cycle capabilities. A memory cycle is initiated by bringing RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensure proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent
ISSI
on the timing relationships between these parameters.
(R)
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last.
Refresh Cycle
To retain data, 512 refresh cycles are required in each 8 ms period. There are two ways to refresh the memory: 1. By clocking each of the 512 row addresses (A0 through A8) with RAS at least once every 8 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.
Memory Cycle
Power-On
After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.
Read Cycle
4
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IS41C16257 IS41LV16257
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VT VCC IOUT PD TA TSTG Parameters Voltage on Any Pin Relative to GND Supply Voltage Output Current Power Dissipation Operation Temperature Storage Temperature 5V 3.3V 5V 3.3V Rating -1.0 to +7.0 -0.5 t0 +4.6 -1.0 to +7.0 -0.5 t0 +4.6 50 1 0 to 70 -40 to +85 -55 to +125 Unit V V mA W C C
ISSI
(R)
Com. Ind.
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND)
Symbol VCC VCC VIH VIH VIL VIL TA Parameter Supply Voltage Supply Voltage Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Ambient Temperature Voltage 5V 3.3V 5V 3.3V 5V 3.3 Com. Ind. Min. 4.5 3.0 2.4 2.0 -1.0 -0.3 0 -40 Typ. 5.0 3.3 -- -- -- -- -- -- Max. 5.5 3.6 VCC + 1.0 VCC + 0.3 0.8 0.8 70 85 Unit V V V V V V C
CAPACITANCE(1,2)
Symbol CIN1 CIN2 CIO Parameter Input Capacitance: A0-A8 Input Capacitance: RAS, UCAS, LCAS, WE, OE Data Input/Output Capacitance: I/O0-I/O15 Max. 5 7 7 Unit pF pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VCC = 5.0V + 10% or Vcc=3.3V 10%.
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IS41C16257 IS41LV16257
ISSI
Test Condition Any input 0V < VIN < Vcc Other inputs not under test = 0V Output is disabled (Hi-Z) 0V < VOUT < Vcc IOH = -2.5 mA IOL = 2.1 mA Speed Min. -10 -10 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 10 10 -- 0.4 2 3 1 2 2 1 230 170 220 160 230 170 230 170 Unit A A V V mA mA mA mA mA
(R)
ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter IIL IIO VOH VOL ICC1 ICC1 ICC2 ICC2 ICC3 Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Stand-by Current: TTL Stand-by Current: TTL
RAS, LCAS, UCAS VIH
ICC4
ICC5
ICC6
Stand-by Current: CMOS Stand-by Current: CMOS Operating Current: Random Read/Write(2,3,4) Average Power Supply Current Operating Current: RAS = VIL, LCAS, UCAS, Fast Page Mode(2,3,4) Cycling tPC = tPC (min.) Average Power Supply Current Refresh Current: RAS Cycling, LCAS, UCAS VIH RAS-Only(2,3) tRC = tRC (min.) Average Power Supply Current Refresh Current: RAS, LCAS, UCAS Cycling CBR(2,3,5) tRC = tRC (min.) Average Power Supply Current
Com. 5V Ind. 5V RAS, LCAS, UCAS VIH Com. 3.3V Ind. 3.3V RAS, LCAS, UCAS VCC - 0.2V 5V RAS, LCAS, UCAS VCC - 0.2V 3.3V RAS, LCAS, UCAS, -35 Address Cycling, tRC = tRC (min.) -60 -35 -60 -35 -60 -35 -60
mA
mA
mA
Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured.The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each fast page cycle. 5. Enables on-chip refresh and address counters.
6
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IS41C16257 IS41LV16257
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless
otherwise noted.) -35 Min. Max. 60 -- -- -- 35 20 6 5 35 11 0 6 0 6 30 -- 35 10 18 10K -- 10K -- -- 28 -- -- -- -- -- -60 Min. Max. 110 -- -- 60 -- 15 -- 30 60 10K 40 -- 10 10K 10 -- 60 -- 20 45 --0 10 -- 0 -- 10 -- 40 --
ISSI
Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(26) CAS Precharge Time(9, 25) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) Units ns ns ns ns ns ns ns ns ns ns -- ns ns ns ns ns
(R)
Symbol tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR
tRAD tRAL tRPC tRSH tCLZ tCRP tOD tOE tOEHC tOEP tOES tRCS tRRH tRCH tWCH tWCR tWP tWPZ tRWL tCWL tWCS tDHR
RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time(27) CAS to Output in Low-Z(15, 29) CAS to RAS Precharge Time(21)
Output Disable Time(19, 28, 29) Output Enable Time(15, 16) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) WE Pulse Widths to Disable Outputs Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS)
12 18 0 8 3 5 3 -- 10 10 5 0 0 0 5 30 5 10 8 8 0 30
20 -- -- -- -- -- 15 10 -- -- -- -- -- -- -- -- -- -- -- -- -- --
15 30 0 15 3 5 3 -- 10 10 5 0 0 0 10 50 10 10 15 15 0 40
30 -- -- -- -- -- 15 15 -- -- -- -- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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7
IS41C16257 IS41LV16257
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless
otherwise noted.) -35 Min. Max. 15 8 0 6 80 45 25 30 12 35 -- 40 3 3 10 8 8 0 -- 1 -- -- -- -- -- -- -- -- -- 100K 21 -- 15 15 -- -- -- -- 8 50 -60 Min. Max. 15 15 0 10 140 80 36 49 25 60 -- 56 3 3 10 10 10 0 -- 1 -- -- -- -- -- -- -- -- -- 100K 34 -- 15 15 -- -- -- -- 8 50
ISSI
Parameter Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) Fast Page Mode READ or WRITE Cycle Time(24) RAS Pulse Width Access Time from CAS Precharge(15) READ-WRITE Cycle Time(24) Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) Output Disable Delay from WE Last CAS going LOW to First CAS returning HIGH(23) CAS Setup Time (CBR REFRESH)(30, 20) CAS Hold Time (CBR REFRESH)(30, 21) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Refresh Period (512 Cycles) Transition Time (Rise or Fall)(2, 3) Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
(R)
Symbol tACH tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tOFF tWHZ tCLCH tCSR tCHR tORD tREF tT
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IS41C16257 IS41LV16257
ISSI
(R)
Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first CAS edge to transition LOW. 21. The last CAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling CAS edge to first rising CAS edge. 24. Last rising CAS edge to next cycle's last rising CAS edge. 25. Last rising CAS edge to first falling CAS edge. 26. Each CAS must meet minimum pulse width. 27. Last CAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters.
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IS41C16257 IS41LV16257
FAST-PAGE-MODE READ CYCLE
ISSI
tRC tRAS tRP
(R)
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH tRRH
UCAS/LCAS
tAR tASR tRAD tRAH tRAL tASC tCAH
ADDRESS WE
Row
tRCS
Column
tRCH
Row
tAA tRAC tCAC tCLC
tOFF(1)
I/O
Open
tOE
Valid Data
tOD
Open
OE
tOES
Don't Care
Note: 1. tOFF is referenced from rising edge of
CAS.
10
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IS41C16257 IS41LV16257
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
ISSI
tRASP tRP
(R)
RAS
tCSH tCAS tCRP tRCD tCP tPRWC tCAS tCP tRSH tCAS tCRP
UCAS/LCAS
tAR tRAH tASR tRAD tASC tCAH tCPWD tASC tAR tCWL tRWD tAWD tCWD tCAH tCPWD tRAL tCAH tASC
ADDRESS
Row
Column
Column
tCWL tAWD tCWD
Column
tCWL tRWL tWP tAWD tCWD
tRCS
tWP
tWP
WE
tAA tCAC tCAC tOEA tOEA tAA tCAC tOEA tAA
OE
tRAC tCLZ
tOEZ tOED tDH tDS tCLZ
OUT IN OUT
tOEZ tOED tDH tDS
IN
tOEZ tOED tDH tCLZ
OUT IN
tDS
I/O0-I/O15
Don't Care
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IS41C16257 IS41LV16257
FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE)
tRC tRAS tRP
ISSI
(R)
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH
UCAS/LCAS
tAR tASR tRAD tRAH tASC tRAL tCAH tACH
ADDRESS
Row
Column
tCWL tRWL tWCR tWCS tWCH tWP
Row
WE
tDHR tDS tDH
I/O
Valid Data
Don't Care
12
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IS41C16257 IS41LV16257
ISSI
tRWC tRAS tRP
(R)
FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH
UCAS/LCAS
tAR tASR tRAD tRAH tRAL tASC tCAH tACH
ADDRESS
Row
tRCS
Column
tRWD tCWD tAWD
Row
tCWL tRWL tWP
WE
tAA tRAC tCAC tCLZ tDS tDH
I/O
Open
tOE
Valid DOUT
tOD
Valid DIN
Open
tOEH
OE
Don't Care
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IS41C16257 IS41LV16257
FAST PAGE MODE EARLY WRITE CYCLE
ISSI
tRASP tRP tRHCP tRSH tCAS tCP tCRP
(R)
RAS
tCSH tCAS tCRP tRCD tCP tPC tCAS
UCAS/LCAS
tAR tRAL tRAH tASR tRAD tASC tCAH tASC tAR tCWL tWCS tWP tWCH tWCS tWP tCAH tASC tCAH
ADDRESS
Row
Column
Column
tCWL tWCH tWCS
Column
tCWL tWCH tWP
WE
tWCR
OE
tDHR tDS tDH tDS tDH tDS tDH
I/O0-I/O15
Valid DIN
Valid DIN
Valid DIN
Don't Care
14
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IS41C16257 IS41LV16257
AC WAVEFORMS READ CYCLE (With WE-Controlled Disable)
RAS
tCSH tCRP tRCD tCAS tCP
ISSI
(R)
UCAS/LCAS
tAR tASR tRAD tRAH tASC tCAH tASC
ADDRESS WE
Row
tRCS
Column
tRCH tRCS
Column
tAA tRAC tCAC tCLZ
tWHZ
tCLZ
I/O
Open
tOE
Valid Data
Open
tOD
OE
Don't Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) RAS
tRC tRAS tRP
RAS
tCRP tRPC
UCAS/LCAS
tASR tRAH
ADDRESS I/O
Row Open
Row
Don't Care
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IS41C16257 IS41LV16257
ISSI
tRP tRAS tRP tRAS
(R)
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
RAS
tRPC tCP tCHR tCSR tRPC tCSR tCHR
UCAS/LCAS I/O Open
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAS tRP tRAS
RAS
tCRP tRCD tRSH tCHR
UCAS/LCAS
tAR tASR tRAD tRAH tASC tRAL tCAH
ADDRESS
Row
Column
tAA tRAC tCAC tCLZ tOFF(2)
I/O
Open
tOE tORD
Valid Data
Open
tOD
OE
Don't Care
Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
16
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IS41C16257 IS41LV16257
ORDERING INFORMATION IS41C16257 Commercial Range: 0C to 70C
Speed (ns) Order Part No. 35 60 IS41C16257-35K IS41C16257-35T IS41C16257-60K IS41C16257-60T Package 400-mil SOJ 400-mil TSOP (Type II) 400-mil SOJ 400-mil TSOP (Type II)
ISSI
ORDERING INFORMATION IS41LV16257 Commercial Range: 0C to 70C
Speed (ns) Order Part No. 35 60 IS41LV16257-35K IS41LV16257-35T IS41LV16257-60K IS41LV16257-60T Package 400-mil SOJ 400-mil TSOP (Type II) 400-mil SOJ 400-mil TSOP (Type II)
(R)
Industrial Range: -40C to 85C
Speed (ns) Order Part No. 35 60 IS41C16257-35KI IS41C16257-35TI IS41C16257-60KI IS41C16257-60TI Package 400-mil SOJ 400-mil TSOP (Type II) 400-mil SOJ 400-mil TSOP (Type II)
Industrial Range: -40C to 85C
Speed (ns) Order Part No. 35 60 IS41LV16257-35KI IS41LV16257-35TI IS41LV16257-60KI IS41LV16257-60TI Package 400-mil SOJ 400-mil TSOP (Type II) 400-mil SOJ 400-mil TSOP (Type II)
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
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